The invention relates to a circuit arrangement for synchronizing a frequency--controllable oscillator with the frequency of a carrier in an input signal, said circuit arrangement comprising a PLL circuit in which the phases of the input signal and a signal derived from the controllable oscillator are compared in a phase discriminator whose output signal, which is dependent on the phase difference, is applied to a control input of the oscillator via a filter.
Circuit arrangements of this type are known, for example, the monolithic integrated circuit TDA 1578 A designed as a stereo decoder for a radio receiver comprises such a circuit. The filter in the PLL circuit is dimensioned in such a way that a capture range of approximately 3% of the input signal frequency (19 kHz) is obtained. On the one hand, this compensates for variations of the free running frequency of the oscillator, caused by variations of the properties of the components and temperature fluctuations of the circuit, and on the other hand the PLL circuit is prevented from locking in on signal components whose frequency differs from the frequency of the pilot signal.
In order that such a small capture range is sufficient, it is necessary to impose strict tolerances on the components which determine the free running frequency of the controlled oscillator, and moreover an adjustment is to be performed, for example by means of a potentiometer.
It is an object of the present invention to realise a circuit arrangement of the type described in the opening paragraph in such a way that an adjustment is not necessary.